Abstract: Power consumption and area are the important parameters to be considered for designing low power applications. This paper proposes the design of low power universal shift register using pipe logic. Since flip flops are an inherent building block in universal shift register, various flip flops are surveyed and implemented in PIPO shift register. Flip flop using pipe logic is considered based on the comparison of power and area. Finally, a low power universal shift register is designed using pipe logic. The proposed USR is simulated with different clock frequencies ranging from 100 MHz to 500MHz. Simulation of these flip flops and the universal shift register is done using Tanner tool at 180nm technology. Further, the average power and the PDP are improved by 33% and 27% when compared with existing design respectively. So the proposed design is suitable for low power and high performance applications.

Keywords: Flip-flops, Shift register, power, delay, PDP.